1. Technical Field:
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for transferring data signals between devices connected to a bus. Still more particularly, the present invention relates to a method and apparatus for reducing problems associated with the skew when transferring data between devices connected to a bus.
2. Description of the Related Art:
Data processing systems, such as work stations, servers, and personal computers, are being used in many aspects of business and personal life. The users of these systems demand and expect high-speed performance from these computers. Many components of the data processing system have been increased in speed to increase performance. For example, processor speeds have been rapidly increasing. In addition, the bus used to interconnect various components within a computer system and transfer signals between them has been another component in which speed has been increased. A bus is commonly employed to interconnect modules of a computer system and transfer signals between them to carry out desired operations within the computer system. In addition, the bus is a key element whose characteristics, such as speed, has a major impact on the overall performance of the computer system. The high-speed performance of interface busses, such as Ultra3 SCSI, which is currently under development, increase with improvements in technology. A difficult design task is to assure that multiple signals on parallel communication media have consistent timing, given factors indicating minute but significant differences in the details of packaging construction, socket and connection variation, PC board variation and variations in the SCSI bus itself.
One problem with increasing speeds in busses, such as SCSI buses, is skew. Skew is the differences between the propagation delays of two or more signals passing through multiple paths in a device or along a set of parallel signal lines. For proper operation of the computer system, clock signals should arrive at the interface circuitry at the same time; otherwise, reliable data transmission is not ensured. For example, if a module receiving data is xe2x80x9cclockedxe2x80x9d later than others, the earlier clocked modules may overwhelm the data before it is stored at its proper destination. The lack of simultaneity in reception of the clock signals relative data signals at the modules, i.e., clock skew, directly increases the amount of time that the data must remain stable on the bus; this, in turn, increases the time required for each data transfer on the bus and, thus reduces the speed of the bus.
The amount of clock skew introduced into a computer system may be caused by the variations in propagation delays among clock receiver chips of the system. In digital logic applications using transistors, a transistor switches xe2x80x9conxe2x80x9d, when saturated, and xe2x80x9coffxe2x80x9d, when non-conducting, to generate full swings between power supply voltages. The resulting output voltage xe2x80x9csignalsxe2x80x9d represent corresponding high and low states. Propagation delay, which affects the switching speed of the transistor, is highly dependent upon variations in the fabrication process of the chip. In addition, the applied voltage, the operating temperature environment and the loading conditions of the chip affect its performance.
Cooperating sequential logic circuits that each perform several routine operations and that are each controlled by derivatives of a common clock signal are present in data processing systems. The clock signals must be synchronized at locations within the system if the system is to function optimally. Although the individual clock signals may have a common source, they often do not arrive at their intended destination in proper synchronism, due to variations in signal propagation delay for each destination. Thus, combining several complex sequential logic circuits within a system presents a challenge with respect to synchronizing the time frames of each of the circuits with each other.
As integration levels of microelectronic circuits and system complexity continues to increase, the routing or distribution of a master system clock becomes more critical. This problem is exacerbated in view of ever increasing clock rates. Thus, clock distribution in a complex integrated circuit requires careful selection of routing scheme, including such considerations as distribution topography across the circuit, propagation delays in routing the clock signal to all elements on the circuit, desired set up and hold times and variations in system design parameters, such as system clock rate, that can affect circuit operation.
Because synchronous sequential logic circuits change states only at the rising or falling edge of a synchronous clock signal, proper circuit operation requires that any external input signals to the synchronous sequential logic circuit must occur with the proper set up time and hold time requirements relative to the designated clock edge. The set up time is the period of time during which a system or component is being prepared for a specific operation. To satisfy a set up time, the data is required to be settled by a predetermined time before the clock edge. The predetermined time is called the xe2x80x9cset upxe2x80x9d time. The xe2x80x9chold timexe2x80x9d is the predetermined time that the data is required to be held after the clock edge. The predetermined time is called the hold time. However, in a system comprised of a sequential logic circuit having a master system clock that operates the several diverse system circuits, a problem exists with skew between the system clock and the destination clock signals propagated through the various circuits. Such a problem is especially evident with bus systems, such as a SCSI bus with various adapters or components using the SCSI bus to transfer data.
Thus, it would be advantageous to have an improved method and apparatus for reducing skew in a system containing devices connected to a bus in which data is sent between the devices.
Another problem with the conventional bus configuration is matching the correct terminating impedance to the bus lines. While the proper termination can be determined for a specific bus after some testing, the impedance of the terminators changes with temperature because the resistors used are not temperature stable. As the bus temperature, and hence the temperature of the terminating resistors change, so does the impedance. Bus termination becomes more crucial for a bus when the number of peripherals increase and in cases when clock skew introduced into a computer system by the variations in propagation delays among clock receiver chips of the system is near the operating tolerance of the bus.
Thus, it would be advantageous to have an improved method and apparatus for stabilizing the impedance of resistors in a bus termination.
Another problem associated with transmitting data is the inter-symbol interference (ISI) problem associated with high speed parallel bus configurations such as the parallel SCSI bus. The ISI problem which results from excess capacitance of the SCSI bus, which becomes worse as the number of peripherals attached to the bus increases. The bus requires charging after being discharged with a series of ones or zeros. A xe2x80x9cshort pulsexe2x80x9d occurs immediately subsequent to a series of three or more consecutive ones or zeros.
Thus, it would be advantageous to have an improved method and apparatus for recognizing when the current driver needs an extra boost to increase the amplitude of a short pulse.
The present invention discloses a method and apparatus for using a variable delay for reducing the skew on a bus, stabilizing bus terminating impedance and reducing inter-symbol interference. A training program trains the host transmitter for optimal skew compensation at a target receiver by identifying an optimal delay value determined by the operational data window. For each bus line, the host sends out a plurality of data patterns, each at a slightly different timing delay, which are returned or echoed back from the target device. The operational data window is defined on each line by the delay timings at which valid data patterns are returned from the target. Once the operational data window has been defined for each line, an optimal delay value, usually the mid-delay in the operational window, for the clock may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized. The output of a phase locked loop is used for controlling the impedance in a bus terminator. The bus terminator includes voltage variable resistors which are controlled by the control voltage from the phase locked loop. The control system for the terminator includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period. The inter-symbol interference problem is reduced be detecting a data sequence indicating when a boost is needed on a xe2x80x98short pulsexe2x80x99, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude.